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Physical Design Engineer - Graduate Intern

at Intel in Oklahoma City, Oklahoma, United States

Job Description

Job Description

Role and Responsibilities:

The world is transforming – and so is Intel. Here at Intel, we believe the world needs technology that can enrich the lives of every person on earth. We work every single day to design and manufacture silicon products that empower people’s digital lives. Do you love to solve technical challenges that no one has solved yet? Do you enjoy working with cross functional teams to deliver solutions for products that impact customers lives? If so, Come join us to do something wonderful.

Intel’s IP group is looking for a Physical Design Engineer to contribute in a high-performance IP space. We are designing innovative IP solutions across multiple technologies and unique architectures that fuels Intel’s servers, clients, and graphics microprocessors.

As a Graduate Intern your responsibilities may include, but not be limited to:

+ You will collaborate with architects, logic designers, and analog engineers in evaluating implementation details of complex design features.

+ You will perform all aspects of the SoC design flow from high-level design through synthesis, place and route, timing analysis and power reduction.

+ Family and/or block-level floor planning, Power supply and power grid planning and analysis, Logic synthesis of design blocks, Formal Equivalence Verification (FEV), Clocking network planning and analysis, Auto Place-and-Route (APR) using Synopsys ICC tools, Timing verification using Synopsys Prime Time, Physical verification – Layout vs. Schematic (LVS), Design Rule Checks (DRC), Electrical Rule Checks (ERC), and Design for Manufacturability checks (DFM), Reliability Verification Debug and resolution of integration issues at parent level.

+ Completion of design reviews and design signoff flows and assist in the preparation of the full-chip layout design database for introduction to manufacturing.

Candidate should also possess the following behavioral traits:

+ Excellent analytical and problem-solving skills

+ Strong verbal/written communication skills

+ Effective team player with continuous learning mindset

+ Willingness to balance multiple tasks

+ Willingness to work in a fast-paced environment and have as much fun and growth as possible in the process

Applicants for this internship should be able to start between March 2024 and June of 2024 and be available as a full-time intern for 3-6 months. This will be a virtual internship.

Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

Candidate must be pursuing a Master’s or Ph.D. degree in Electrical Engineering or a related field.

Theoretical knowledge or qualifying course work in:

+ SoC Design Flows: Experience with industry standard EDA tools doing RTL to GDS design.

Preferred Qualifications:

+ VLSI circuits, design techniques, and sub-micron CMOS technologies

+ Designing high-speed, low-power digital circuits, floor planning, timing convergence and layout verification

+ Logic synthesis and automated place and route tools

+ Computer architecture and logic design fundamentals

+ Hardware description languages such as Verilog or System Verilog

Requirements listed could be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.

Inside this Business Group

In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel’s products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore’s Law and groundbreaking innovations. DEG is Intel’s engineering group, supplying silicon to business units as well as other engineering teams. As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here. (https://jobs.intel.com/en/benefits)

Annual Salary Range for jobs which could be performed in US, Colorado, New York, Washington, California: $63,000.00-$166,000.00

*Salary range dependent on a number of factors including location and experience

Working Model

This role is available as a fully home-based and generally would require you to attend Intel sites only occasionally based on business need. This role may also be available as our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.

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Job Posting: JC256794560

Posted On: Mar 14, 2024

Updated On: Jun 25, 2024

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